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is62/65 wv102416eall is62/65 wv102416ebll integrated silicon solution, inc. - www.issi.com 1 rev. a 12/12 /2014 1m x16 low voltage, ultra low power cmos static ram key features ? hi gh - speed access time: 45ns, 55ns ? cmos low power operation C 30 mw (typical) operating C 12 w (typical) cmos standby ? ttl compatible interface levels ? single power supply C 1.65v 1.98 v vdd (62/65wv102416 eall) C 2.2 v -- 3.6v vdd (62/65wv102416 ebll) ? data control for upper and lower bytes ? industrial and automotive temperature support description the IS62WV102416EALL/bll and is 65wv102416eall/bll are low power , 16m bit static rams organized as 1 0 24k words by 16bits. it is fabricated using 's high - performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields high - performanc e and low power consumption devices. when is high (deselected) or when cs2 is low (deselected) or when is low , cs2 is high and both and are high, the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. easy memory expansion is provided by using chip enable and output enable inputs. the active low write enable contr ols both writing and reading of the memory. a data byte allows upper byte and lower byte ( access. the IS62WV102416EALL/bll and is65wv102416eall/bll are packaged in the jedec standard 48 - pin bga (6mm x 8mm). b lock diagram copyright ? 201 4 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specification and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the fa ilure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. pr oducts are not authorized for use in such applications unless integrated silicon solution, inc. receives written as surance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances january 2015
is62/65 wv102416eall is62/65 wv102416ebll integrated silicon solution, inc. - www.issi.com 2 rev. a 12/12 /2014 pin configurations 48 - pin bga pin descriptions C 2 cs option a0 - a19 address inputs i/o0 - i/o15 data inputs/outputs , cs2 chip enable input s output enable input write enable input lower - byte control (i/o0 - i/o7) upper - byte control (i/o8 - i/o15) nc no connection vdd power gnd ground 1 2 3 4 5 6 a a0 a1 a2 cs2 b i/o8 a3 a4 i/o0 c i/o9 i/o10 a5 a6 i/o1 i/o2 d gnd i/o11 a17 a7 i/o3 vdd e vdd i/o12 nc a16 i/o4 gnd f i/o14 i/o13 a14 a15 i/o5 i/o6 g i/o15 a19 a12 a13 i/o7 h a18 a8 a9 a10 a11 nc
is62/65 wv102416eall is62/65 wv102416ebll integrated silicon solution, inc. - www.issi.com 3 rev. a 12/12 /2014 function description sram is one of random access memories. each byte or word has an address and can be accessed randomly. sram has three diffe rent modes supported. each function is described below with truth table. standby mode device enters standby mode when deselected ( high or c s 2 low or both and are high). the input and output pins (i/o0 - 15) are p laced in a high impedance state. the current consumption in this mode will be either isb1 or isb2 depending on the input level. cmos input in this mode will maximize saving power. write mode write operati on issues with chip selected ( low a nd cs2 high) and write enable ( ) input low. the input and output pins(i/o0 - 15) are in data input mode. output buffers are c losed during this time even if is low. and enables a b yte write feature. by e n abling low, data from i/ o pins (i/o0 through i/o7) are written into the location speci fied on the address pins. and with being low, data from i/o pins (i/o8 through i/o15) are written into the location . read mode read operation issues with chip selected ( low and c s 2 high) and write enable ( ) input high. when is low, output buff er turns on to make data output. any input to i/o pins during read mode is not permitted. and enables a byte r ead feature. by enabling low, data from memo ry appears on i/o0 - 7. and with being low, data from memory appears on i/o8 - 15. in the read mode, output buffers can be turned off by pulling high . in this mode, internal device operates as read but i/os are in a high impedance state. since device is in read mode, active current is used. truth table mode cs2 i/o0 - i/o7 i/o 8 - i/o15 vdd current not selected h x x x x x high - z high - z isb1,isb2 x l x x x x high - z high - z x x x x h h high - z high - z output disabled l h h h l x high - z high - z icc l h h h x l high - z high - z read l h h l l h dout high - z icc l h h l h l high - z dout l h h l l l dout dout write l h l x l h din high - z icc l h l x h l high - z din l h l x l l din din
is62/65 wv102416eall is62/65 wv102416ebll integrated silicon solution, inc. - www.issi.com 4 rev. a 12/12 /2014 absolute maximum rat ings and operating range absolute maximum rat ings (1) symbol parameter value unit vter m terminal voltage with respect to gnd C 0.2 to + 3.9 (v dd +0. 3 v) v tbias temperature under bias C 55 to +125 ? c v dd v dd related to gnd C 0.2 to + 3 . 9 (v dd +0. 3 v) v tstg storage temperature C 65 to +150 ? c i out dc output current (low) 20 ma note s: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section s of this specification is not imp lied. exposure to absolute maximum rat ing conditions for extended periods may affect reliability. operating range (1) range device marking ambient temperature v dd (min) v dd (typ ) v dd (max) commercial is62 wv102416eall 0 ? c to +70 ? c 1.65v 1.8 v 1.98 v industrial is62 wv102416eall - 40 ? c to +85 ? c 1.65v 1.8 v 1.98 v automotive is65 wv102416eall - 40 ? c to +125 ? c 1.65v 1.8 v 1.98 v commercial is62 wv102416ebll 0 ? c to +70 ? c 2.2 v 3. 3 v 3.6 v industrial is62 wv102416ebll - 40 ? c to +85 ? c 2.2 v 3. 3 v 3.6 v automotive is65 wv102416ebll - 40 ? c to +125 ? c 2.2 v 3. 3 v 3.6 v note: 1. full device ac operation assumes a 100 s ramp time from 0 to vcc(min) and 200 s wait time after vcc stabilization. pin capacitance (1) parameter symbol test condition max units input capacitance c in t a = 25 c, f = 1 mhz, v dd = v dd (typ) 10 pf dq capacitance (io0 C io15) c i/o 10 pf note: 1. these parameters are guaranteed by design and tested by a sample basis only. thermal characterist ics (1) parameter symbol rating units thermal resistance from junction to ambient (airflow = 0 m/s) r ja 43.05 c/w thermal resistance from junction to case r jc 5.75 c/w note: 1. t hese parameters are guaranteed by design and tested by a sample basis only.
is62/65 wv102416eall is62/65 wv102416ebll integrated silicon solution, inc. - www.issi.com 5 rev. a 12/12 /2014 electrical character istics is62 (5) wv102416eall dc electrical character istics - i (over the o perating range ) symbol parameter test conditions min. max. unit v oh output high voltage i oh = - 0.1 ma 1.4 v v ol output low voltage i ol = 0.1 ma 0.2 v v ih ( 1 ) input high voltage 1.4 v dd + 0.2 v v il ( 1 ) input low voltage C 0.2 0.4 v i li input leakage gnd < v in < v dd C 1 1 a i lo output leakage gnd < v in < v dd , o utput disabled C 1 1 a note s: 1. vill(min) = - 1 .0v ac (p ulse width < 10ns ) . not 100% tested. vihh (max ) = vdd + 1 .0v ac (p ulse width < 10ns ) . not 100% tested. is62 (5) wv102416ebll dc electrical charac teristics - i (over the operating range) symbol parameter test conditions min. max. unit v oh output high voltage 2.2 v dd < 2.7, i oh = - 0.1 ma 2.0 v 2. 7 v dd 3 . 6, i oh = - 1 . 0 ma 2.4 v v ol output low voltage 2.2 v dd < 2.7, i ol = 0.1 ma 0. 4 v 2. 7 v dd 3 . 6, i ol = 2 .1 ma 0. 4 v v ih ( 1 ) input high voltage 2.2 v dd < 2.7 1. 8 v dd + 0. 3 v 2. 7 v dd 3 . 6 2.2 v dd + 0. 3 v v il ( 1 ) input low voltage 2.2 v dd < 2.7 C 0. 3 0. 6 v 2. 7 v dd 3 . 6 C 0. 3 0. 8 v i li input leakage gnd < v in < v dd C 1 1 a i lo output leakage gnd < v in < v dd , o utput disabled C 1 1 a notes: 1. vill(min) = - 2 .0v ac (p ulse width < 10ns ) . not 100% tested. vihh (max) = vdd + 2 .0v ac (p ulse width < 10ns ) . not 100% tested .
is62/65 wv102416eall is62/65 wv102416ebll integrated silicon solution, inc. - www.issi.com 6 rev. a 12/12 /2014 is62 (5) wv102416eall dc electrical charac teristics - ii for power (over the operating range) symbol parameter test conditions grade typ. max. unit icc v dd dynamic operating supply current v dd =v dd (max), i out =0ma, f=f max com. 6 1 2 ma ind. - 1 2 auto. - 12 icc1 v dd static operating supply current v dd =v dd (max), i out = 0ma, f=0hz com. 3 6 ma ind. - 6 auto. - 6 isb1 cmos standby current (cmos inputs) v dd =v dd (max), (1) 0v cs2 0.2v or (2) v dd - 0.2v, cs2 v dd - 0.2v or (3) and v dd - 0.2v 0.2v, cs2 v dd - 0.2v com. 30 50 a ind. - 65 a auto. - 1 65 a note : typical values are included for reference only and are not guaranteed or tested. typical values are mea sured at vdd = vdd(typ), ta = 25 ? c is62 (5) wv102416ebll dc electrical charac teristics - ii for power (over the operating range) symbol parameter test conditions grade typ. max. unit icc v dd dynamic operating supply current v dd =v dd (max), i out =0ma, f=f max com. 6 1 2 ma ind. - 1 2 auto. - 12 icc1 v dd static operating supply current v dd =v dd (max), i out = 0ma, f=0hz com. 3 6 ma ind. - 6 auto. - 6 isb1 cmos standby current (cmos inputs) v dd =v dd (max), (1) 0v cs2 0.2v or (2) v dd - 0.2v, cs2 v dd - 0.2v or (3) and v dd - 0.2v 0.2v, cs2 v dd - 0.2v com. 30 50 a ind. - 65 a auto. - 1 65 a note : typical values are included for reference only and are not guaranteed or tested. typical values are measured at vdd = vdd(typ ), ta = 25
is62/65 wv102416eall is62/65 wv102416ebll integrated silicon solution, inc. - www.issi.com 7 rev. a 12/12 /2014 ac characteristics ( 6) (over operating rang e) read cycle ac characteristics parameter symbol 4 5ns 55ns unit notes min max min max read cycle time trc 4 5 - 55 - ns 1,5 address access time taa - 4 5 - 55 ns 1 output hold time toha 8 - 8 - ns 1 , cs2 access time tacs1/tacs2 - 4 5 - 55 ns 1 access time tdoe - 2 2 - 25 ns 1 to high - z output thzoe - 18 - 18 ns 2 to low - z output tlzoe 5 - 5 - ns 2 , cs2 to high - z output thzcs/ /thzcs2 - 18 - 18 ns 2 , cs2 to low - z output tlzcs /tlzcs2 10 - 10 - ns 2 , access time tba - 45 - 55 ns 1 , to high - z output thzb - 18 - 18 ns 2 , to low - z output tlzb 10 - 10 - ns 2 write cycle ac characteristics parameter symbol 4 5ns 55ns unit notes min max min max write cycle time twc 4 5 - 55 - ns 1,3,5 ,cs2 to write end tscs1/tscs2 35 - 40 - ns 1,3 address setup time to write end taw 35 - 40 - ns 1,3 address hold from write end tha 0 - 0 - ns 1,3 address setup time tsa 0 - 0 - ns 1,3 , / valid to end of write tpwb 35 - 40 - ns 1,3 pulse width tpwe 35 - 40 - ns 1,3,4 data setup to write end tsd 28 - 28 - ns 1,3 data hold from write end thd 0 - 0 - ns 1,3 low to high - z output thzw e - 18 - 18 ns 2,3 high to low - z output tlzwe 10 - 10 - ns 2,3 notes: 1. tested with the load in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady - state voltage. thzoe, thzcs, thzb, and thzwe transitions are measured when the output enters a high impedance state. not 100% tested. 3. the internal write time is defined by the ov erlap of =low, cs2=high, ( or )=low, and =low. all four conditions must be in valid states to initiate a write, but any condition can go inactive to terminate the write. the data input setup and hold timing ar e referenced to the rising or falling edge of the signal that terminates the write. 4. tpwe > thzwe + tsd when oe is low. 5. address inputs must meet v ih and v il spec during this period. any glitch or unknown inputs are not permitted. unknown input with standby mode is acceptable. 6. data retention characteristics are defined later in data retention characteristics.
is62/65 wv102416eall is62/65 wv102416ebll integrated silicon solution, inc. - www.issi.com 8 rev. a 12/12 /2014 ac test conditions ( over the operating r ange) parameter symbol conditions units input rise time t r 1.0 v/ns input fall time t f 1.0 v/ns output timing reference level v ref ? v tm v output load conditions refer to figure 1 and 2 output load conditio ns figures figure1 figure2 parameters v dd =1.65~1.98v v dd =2.2~2.7v v dd =2.7~3.6v r1 13500 ? 16667? 1103 ? r2 10800 ? 15385? 1554 ? v tm v dd vdd vdd 30pf, including jig and scope r2 r1 v tm output 5pf, including jig and scope r2 r1 v tm output
is62/65 wv102416eall is62/65 wv102416ebll integrated silicon solution, inc. - www.issi.com 9 rev. a 12/12 /2014 timing diagram read cycle no. 1 (1,2) (address controlled) ( = =vil, cs2= =vi h ) read cycle no. 2 (1 , 3) ( , cs2, , and & controlled) notes: 1. is high for read cycle. 2. the device is continuously selected. , , , or =vil.cs2= =vih. 3. address is valid prior to or coincident with low transition . trc address cs2 , i/o0 - 15 taa tdoe data valid low - z high - z tlzb tba thzb thzcs1/ thzcs2 tlzcs1/ tlzcs2 tacs1/tacs2 tlzoe thzoe toha trc address i/o0 - 15 taa toha toha data valid previous data valid low - z low - z
is62/65 wv102416eall is62/65 wv102416ebll integrated silicon solution, inc. - www.issi.com 10 rev. a 12/12 /2014 write cycle no. 1 ( controlled, = high or low) notes: 1. thzwe is based on the assumption when tsa=0ns after read operation. actual dout for thzwe may not appear if goes high before write cycle. thzoe is the time dout goes to high - z after goes high. 2. during this period the i/os are in output state. do not apply input signals . write cycle no. 2 ( controlled: is high during write cycle) notes: 1. thzwe is based on the assumption when tsa=0ns after read operation. actual do ut for thzwe may not appear if goes high before write cycle. thzoe is the time dout goes to high - z after goes high. 2. during this period the i/os are in output state. do not apply input signals. twc address cs2 , dout tscs1 taw tlzwe thzwe tsa tpwe tpwb tscs2 din tha tsd thd data valid data undefined (2) data undefined (1) twc address cs2 dout tscs1 taw tlzwe thzwe tsa tpwe tscs2 din tha tsd thd data valid data undefined (2) data undefined (1) high - z tpwb
is62/65 wv102416eall is62/65 wv102416ebll integrated silicon solution, inc. - www.issi.com 11 rev. a 12/12 /2014 write cycle no. 3 ( controlled: is low during writ e cycle) notes: 1. if is low during write cycle, thzwe must be met in the application. do not apply input signal during this period. data output fr om the previous read operation will drive io bus. twc address cs2 dout tscs1 taw tlzwe thzwe tsa tpwe tscs2 din tha tsd thd data valid data undefined (1) data undefined (1) high - z low tpwb
is62/65 wv102416eall is62/65 wv102416ebll integrated silicon solution, inc. - www.issi.com 12 rev. a 12/12 /2014 write cycle no. 4 ( & controlled) notes: 1. if is low during write cycle, thzwe must be met in the application. do not apply input signal during this period. data output fr om the previous read operation will drive io bus. 2. du e to the restriction of note1, is recommended to be high during write period. 3. note stays low in this ex ample. if toggles, tpwe and thzwe must be considered. twc twc cs2 low high data undefined (1) data valid data valid thd tsd thd tlzwe thzwe tpwb tha tha tsa address dout din tpwb tsd tsa
is62/65 wv102416eall is62/65 wv102416ebll integrated silicon solution, inc. - www.issi.com 13 rev. a 12/12 /2014 data retention characteristics symbol parameter test condition option min. typ. (2) max. unit v dr v dd for data retention see data retention waveform is62 (5) wv102416eall 1. 5 - v is62 (5) wv102416ebll 1 .5 - v i dr data retention current v dd = v dr (min) , (1) 0v cs2 0.2v, or (2) v dd C 0.2v, cs2 v dd - 0.2v (3) and v dd - 0.2v, 0.2v, cs2 v dd - 0.2v com. - - 50 ua ind. - - 65 auto - - 1 65 t sdr data retention setup time see data retention waveform 0 - - ns t rdr recovery time see data retention waveform trc - - ns note: 1. if >vdd C 0.2v, all other inputs including cs2 and and must meet this condition. 2. typical values are measured at v dd =v dr(min) , t a = 25 and not 100% tested. data retention wavef orm ( controlled) data retention wavef orm (cs2 controlled) data retention mode t rdr t sdr v dd gnd v dr > v dd - 0.2v data retention mode t rdr t sdr v dd gnd v dr cs2 cs2 < 0.2v
is62/65 wv102416eall is62/65 wv102416ebll integrated silicon solution, inc. - www.issi.com 14 rev. a 12/12 /2014 ordering information 1.65v~1.98v industrial r ange ( - 40 ? ? speed (ns) order part no package 55 is62 wv102416eall - 5 5b i 48 - pin bga is62 wv102416eall - 5 5b li 48 - pin bga , lead - free 1.65v~1.98v automotive (a3) r ange ( - 40 ? ? speed (ns) order part no package 55 is6 5 wv102416eall - 5 5ba3 48 - pin bga is6 5 wv102416eall - 5 5b l a3 48 - pin bga , lead - free 2.2v~3.6v industrial r ange ( - 40 ? ? speed (ns) order part no package 45 is62 wv102416ebll - 4 5b i 48 - pin bga is62 wv102416ebll - 4 5b li 48 - pin bga , lead - free 55 is62 wv102416ebll - 55 b li 48 - pin bga , lead - free 2.2v~3.6v automotive (a3) r ange ( - 40 ? ? speed (ns) order part no package 55 is6 5 wv102416ebll - 5 5 ba3 48 - pin bga is6 5 wv102416ebll - 5 5 bla3 48 - pin bga , lead - free
is62/65 wv102416eall is62/65 wv102416ebll integrated silicon solution, inc. - www.issi.com 15 rev. a 12/12 /2014

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